Responsibilities:
- RTL synthesis
- Large scale Integrated Circuit Place & Route with advance technology nodes (like 40nm)
- Timing analysis and fixing, timing signoff
- Design for Test
- Physical Signoff (DRC & LVS)
- Deliver SOC chips within schedule
- Qualifications
MUST HAVE:
- Have clear and good concept for digital IC design, including timing and semiconductor knowledge.
- Good team-player with open-minded and proactive working style
- Good communication skills in English both writing and verbal
- BSEE or above in related field
NICE TO HAVE:
- Experiences in EDA tools, specially Place and Route tools is a strong plus
- Experiences in IC design is a strong plus
- Experience in Unix/Linux working environment is a plus
- Experience in TCL, Perl language is a plus
Apply